This invention relates to image sensors, and in particular to image sensors utilizing continuous photodiode layers formed over pixel access and control structures.
Solid state image sensors used in, for example, video cameras are presently realized in a number of forms including charge coupled devices (CCDs) and CMOS image sensors. These image sensors are based on a two dimensional array of pixels. Each pixel includes a sensing element that is capable of converting a portion of an optical image into an electronic signal. These electronic signals are then used to regenerate the optical image on, for example, a liquid crystal display (LCD) or cathode-ray tube (CRT) display.
CMOS image sensors first appeared in 1967. However, CCDs have generally prevailed since their invention in 1970. Both CMOS and CCD solid-state imaging sensors depend on the electrical response that results when silicon is exposed to light. Photons in the visible and near-IR regions of the spectrum have sufficient energy to create free carriers in silicon. The number of electrons released is proportional to the light intensity. Even though both technologies use the same general physical properties, all-analog CCDs dominate vision applications because of their superior dynamic range, low fixed-pattern noise (FPN), and high sensitivity to light.
More recently, however, CMOS image sensors have gained in popularity. CMOS image sensors have benefited from advances in CMOS technology such that they provide several advantages over CCD imagers. Shrinking lithography and advanced signal-processing algorithms set the stage for sensor array, array control, and image processing on one chip produced using well-established CMOS techniques. Typically, the sensor array is formed in a selected region of the chip, and the array control and image processing circuitry is formed around the sensor array. Each CMOS image sensor pixel of a sensor array includes a light sensor formed by diffusing an n-type dopant into a selected region of the silicon chip substrate, and also forming one or more FET switches and an amplifier, along with associated addressing lines, along the perimeter of the diffused light sensor. All of these elements are formed using the same CMOS technology utilized to form the control and image processing circuitry. A typical CMOS pixel size is 5-15 microns, and requires lower bias voltages than that required for CCD image sensors. Therefore, by integrating the sensor array, control and image processing on a single chip and utilizing lower bias voltages, CMOS image sensors are typically lower in cost and power consumption than CCD image sensors.
However, conventional CMOS image sensors that include light-sensing elements (photodiodes) formed in a silicon substrate have some technical disadvantages. In particular, the use of the silicon substrate to form the light-sensing element typically requires the formation of access transistors, metal signal lines, and other structures around the perimeter of the light-sensing element. This reduces the sensitivity because a significant portion of the substrate is screened by the metal lines and other elements, and therefore cannot be used to form light-sensing elements. In addition, the long diffusion length of carriers in the silicon substrate causes cross-talk between adjacent pixels giving reduced spatial resolution.
CMOS image sensors that are fabricated using Thin Film on ASIC (TFA) technology were recently introduced that provide enhanced performance over conventional CMOS image sensors. TFA-type CMOS sensors includes a light sensitive (sensor) material, such as amorphous silicon (a-Si:H), deposited on top of the pixel array (i.e., the access transistors and metal signal lines), thereby increasing the area that can be utilized for light detection by positioning the pixel electronics below the photodiode (sensor) material. The light sensitive material layer is sandwiched between a transparent continuous bias layer (e.g., indium-tin oxide (ITO)) and discrete contact pads (i.e., metal electrodes) associated with each pixel of the array. The contact pad of each pixel is connected to the pixel electronic circuit (e.g., amplifier and one or more access/reset transistors). During operation a bias voltage is applied to the sensor material by the continuous bias layer to create a potential between the continuous bias layer and the individual pixel contact pads through the light sensitive material. Light passing into the light sensitive material frees electrons that generate a current between the pixel contact pad and the continuous bias layer, thereby changing the charge stored on the pixel contact pad. The access transistor of each pixel is periodically turned on to transfer the signal developed in the pixel to the single processor electronics positioned around the array. The signal that is transferred is proportional to the change in charge existing on the pixel contact pad, which in turn is proportional to the amount of light striking the sensor material above that pixel. The benefit of the TFA-type CMOS sensor is that virtually the whole pixel area is light sensitive, and the carrier diffusion and device interaction in the illuminated substrate is eliminated. This structure for the pixel is essentially the same as is used on a-Si:H large area arrays, using the so-called xe2x80x9chigh fill factor approachxe2x80x9d, in which a continuous a-Si:H photodiode is placed on top of the addressing electronics (e.g. R. A. Street et al, MRS Symp. Proc. Vol 377, 757, 1995; see also co-owned U.S. Pat. No. 5,619,033 to Richard Weisfield, entitled xe2x80x9cLayered Solid State Photodiode Sensor Arrayxe2x80x9d). CMOS sensors containing a-Si:H photodiodes have been described by Bohm et al. (e.g. MRS Symp. Proc. Vol 507, 327, 1998).
Although TFA-type CMOS image sensors provide significant advantages over conventional, substrate-based photodiode sensors, additional improvements are needed to optimize image sensor performance. For example, due to the continuous sensor material layer utilized in TFA-type sensors, signal leakage between adjacent pixels is a significant problem that reduces sensor spatial resolution. Further, the sensitivity of TFA-type CMOS image sensors is reduced by reflection of light from the ITO biasing layer, or by light passing through the sensor material without generating any current (i.e., without interacting with the sensor material to free electrons).
Accordingly, what is needed is a TFA-type CMOS image sensor with reduced cross-talk and/or improved light absorption.
The present invention is directed to structural modifications to a TFA-type image sensor array (e.g., a CMOS image sensor array) that facilitate enhanced performance by reducing cross-talk between adjacent pixels, and/or by modifying the light receiving structure of the image sensor to increase light absorption.
In accordance with an embodiment of the present invention, an image sensor array includes a plurality of pixel circuits arranged in rows and columns, each pixel circuit including a continuous sensor layer formed over an array of pixel contact pads, each pixel contact pad being connected by associated pixel circuitry that selectively transfers a charge from the pixel contact pad to an associated data line in response to a control signal transmitted on an associated gate line. The pixel circuitry typically includes an access field effect transistor (FET) controlled by an associated gate line, and an amplifier (e.g., a source follower) connected between the pixel contact and the access transistor. The gate lines are controlled by a scanning control circuit and are arranged such that each gate line controls one row of pixels. The data lines are arranged such that each data line transfers charge from one column of pixels to readout circuitry.
In accordance with a first aspect of the present invention, a series of crisscrossing walls are patterned into an upper passivation layer such that an array of trenches are defined therein. The contact pad of each pixel is formed in an associated trench such that an upper surface of the contact pad is located below the upper edges of the four wall segments surrounding the contact pad. A metal via extends through a lower portion of the passivation layer to connect the pixel contact pad to its associated pixel circuitry. By placing the pixel contact pads into trenches such that each pixel contact pad is separated from adjacent pixel contact pads by the passivation walls, the amount of cross-talk between adjacent pixel contact pads is reduced, thereby increasing image sensor resolution.
In accordance with another aspect of the present invention, an amorphous silicon photodiode layer is formed over the passivation layer such that doped lower portions of the photodiode layer extend into the trenches and are also separated by the passivation walls. The upper edges of the passivation walls define openings through which the pixel contact pads are exposed. The lower portions of the photodiode layer, which are formed on corresponding contact pads, are doped with an n-type dopant to facilitate electrical conduction from the photodiode layer to the pixel contact pad. Located above the lower portions is a continuous central region of undoped a-Si:H material, and above the central undoped region is a continuous upper p-type doped region. A transparent biasing layer (e.g., ITO) is formed over the photodiode layer. To prevent cross-talk between adjacent pixels, the passivation walls are formed such that the lower doped portions of the a-Si:H photodiode layer are located below the upper edges of the passivation walls (i.e., the passivation walls extending into the undoped central region of the photodiode layer). Further, to minimize conduction in the undoped central region of the photodiode layer (particularly along the passivation/photodiode interface), the passivation walls are formed from one of SiO2 or SiON, instead of conventional Silicon-Nitride (Si3N4).
In accordance with another aspect of the present invention, a conductor is formed under the interface regions separating adjacent pixels (e.g., under the passivation walls, described above). The conductor is biased to prevent conduction between adjacent pixel contact pads. The present inventors have determined that, in some instances, the passivation and/or the undoped central region of the photodiode layer located between adjacent pixels act like the channel of a transistor to pass current from one pixel contact pad to an adjacent pixel contact pad. The metal structures placed under the interface regions separating the pixels and biased using a low or negative voltage act as a gate that turns off this effective transistor, thereby preventing leakage (cross-talk) between adjacent pixel contact pads and improving the dynamic range of the image sensor. The metal structure can also be extended under the pixel contact pad to increase the capacitance of each pixel, thereby increasing the capacitance of each pixel.
In accordance with another aspect of the present invention, alternative photodiode materials are utilized in combination with other aspects of the present invention to provide various CMOS image sensors exhibiting improved performance. In one disclosed embodiment, a novel a-Si:H photodiode structure is formed without the lower n-type doped region found in conventional a-Si:H sensors, thereby reducing the occurrence of cross-talk between adjacent pixels.
In accordance with another aspect of the present invention, a non-planar topology is provided under an a-Si:H sensor layer that increases the collection efficiency and absorption of light by the sensor layer. In particular, passivation material is etched to form an inverted, truncated pyramid having sloped walls that meet at a centrally-located primary contact structure, which is connected to an access transistor as described above. Secondary contact structures (e.g., n-type dopant and/or Chrome) are formed on the sloped walls and are connected to the primary contact structure. Formed on the secondary contact structures and primary contact structures is an a-Si:H sensor layer that conforms with the underlying topology. An ITO biasing layer is formed over the a-Si:H sensor layer, and also conforms with the underlying topology. The angle of the sloped walls is selected to increase the number of photons entering the a-Si:H sensor layer. In particular, a light ray at normal or near normal incidence to the plane of the sensor chip will be partly absorbed and partly reflected at the first point of incidence. The absorbed light generates a current between the primary/secondary contact structures and the biasing layer. The reflected light will strike the opposite side of the structure, where more absorption takes place. This reflection/absorption process repeats until the light is substantially absorbed, leading to a significantly higher fraction of the light being absorbed than in a planar structure.
In accordance with another aspect of the present invention, a color filter structure is disclosed that further enhances light absorption.